For decades, monolithic system-on-chip ("SoC") designs defined the semiconductor landscape. Introduced in the 1970s1 and refined over several generations, SoCs allowed designers to integrate processors, memory controllers, accelerators, and I/O onto a single die. This design philosophy enabled performance gains, simplified manufacturing logistics, and kept IP ownership relatively centralized.2 That model is now evolving. As chips approach the physical and economic limits of scaling, integration of all components onto a single die (once an advantage) has become a cost bottleneck.3
"Chiplets" offer a modular response. Each chiplet is a smaller, function-specific die (such as a CPU tile, an I/O hub, a signal processing unit, or a memory block), fabricated independently and integrated using advanced packaging technologies.4 This approach allows for increased flexibility and configurability for design of the full chip stack, enabling designers to combine components made using different manufacturing technologies, integrate off-the-shelf building blocks, and scale systems beyond the physical limits of a single chip.5 Moreover, chiplets have proved especially well-suited for artificial intelligence workloads. Chiplets' modular nature allows companies to integrate dedicated AI accelerators, expand memory bandwidth, and scale compute more efficiently, all critical capabilities for training and deploying large models.6 Chiplet adoption has accelerated in parallel.
With this shift, however, comes a new set of legal implications. Each tile may be owned by a different entity, licensed under different terms, or governed by its own export obligations and IP warranties. Risk is no longer concentrated in a single system owner associated with a fully-integrated SoC. In response, the semiconductor industry is beginning to build the commercial and legal frameworks needed to manage that complexity. Two recent developments, the UCIe standard and Intel's chiplet alliance, illustrate how that process is unfolding.
A. Emergence of Chiplet-Based SSO – UCIe
As chiplet adoption has gained momentum, standard-setting have organizations ("SSOs") began to form around the interface layer (the physical and logical connection between dies in a multi-chip package). The leading SSO in this space is the Universal Chiplet Interconnect Express ("UCIe") Consortium, which launched in 2022, with founding members including Advanced Semiconductor Engineering, Inc., AMD, Arm, Google Cloud, Intel, Meta, Microsoft, Qualcomm, Samsung Electronics, and TSMC.7
UCIe aims to establish a standardized interface for connecting chiplets within a package, mitigating issues surround the lack of standardization in how independently manufactured chiplets talk to each other, which has been a critical barrier to widespread chiplet adoption.Since 2022, UCIe has released three versions of the standard (most recently, version 2.0, released in August 2024), which UCIe describes as "establish[ing] a ubiquitous interconnect at the package level and covers the die-to-die I/O physical layer, Die-to-Die protocols, and software stack which leverage the well-established PCI Express® (PCIe®) and Compute Express Link" (CXL") industry standards."8
As with any widely adopted technical standard, UCIe-compliant chiplets may implicate standard-essential patents ("SEPs") that must be licensed on reasonable and non-discriminatory (RAND) terms to implement the specification.9 In a chiplet context, where no single company controls the entire system, contractual responsibility for SEP clearance is less clear. While UCIe does not adjudicate patent rights or offer a centralized RAND licensing mechanism (unlike SSOs such as MPEG LA or 3GPP), it has nonetheless placed renewed focus on how interface-level IP risk is allocated contractually. As with all standards, contractual risk around UCIe adoption is shaped by how responsibilities and licensing obligations are allocated across the supply chain.
Contracts involving UCIe-compliant chiplets may increasingly be expected to address licensing exposure at the interface. For example, tile suppliers may be required to represent that they hold (or will obtain) appropriate licenses to any standard-essential patents subject to RAND terms. These representations may be tied to flow-down indemnity clauses, obligating the tile supplier to defend or reimburse the integrator if a third party asserts an SEP claim. As UCIe adoption grows, the presence or absence of such clauses could shape risk allocation not only between suppliers and integrators, but also across entire semiconductor supply chains.
B. The Push Toward Ecosystem Norms – Intel's Chiplet Alliance
A parallel development in the chiplet landscape is Intel's effort to create shared norms for how chiplets are sourced, validated, and integrated across vendors. In March 2025, Intel Foundry Services ("IFS") launched the "Chiplet Alliance."10 The alliance is a program aimed "enabling an ecosystem that supports interoperable and secure chiplet implementations."11
Although Intel has not published contractual templates, the Chiplet Alliance serves as a de facto market reference point for ecosystem expectations. Members of the alliance include major players across the semiconductor value chain, such as Arm, Synopsys, Cadence, and Siemens, underscoring the program's ambition to shape commercial norms for chiplet-based integration. By publicly endorsing secure, interoperable tile designs, the Chiplet Alliance serves as a signal to the industry regarding what may constitute acceptable interface practices (even if specific indemnity and warranty terms are currently left unstated).
C. Conclusion
Chiplets promise modularity, reuse, and accelerated innovation. They also fragment IP rights and contractual responsibility. Standards like UCIe and programs like the Chiplet Alliance illustrate how the semiconductor industry is beginning to align its legal architecture with its evolving design architecture.
For attorneys working in semiconductor transactions, the growing use of chiplets means that interface-level diligence is becoming more relevant. Provisions addressing indemnity, licensing representations, and SEP-related obligations are taking on greater importance in contract negotiations. As chiplet adoption becomes more widespread, aligning agreements with emerging standards and ecosystem expectations will be increasingly important for mitigating legal and commercial risk.
Footnotes
1. 1974: Digital Watch Is First System‑On‑Chip Integrated Circuit, The Silicon Engine, Computer History Museum, (last visited July 16, 2025), https://www.computerhistory.org/siliconengine/digital-watch-is-first-system-on-chip-integrated-circuit/
2. Jean-Charles Rochet & Jean Tirole, Platform Competition in Two-Sided Markets, SSRN Working Paper No. 259878, at 14 (2001), https://papers.ssrn.com/sol3/papers.cfm?abstract_id=259878.
3. Saif M. Khan & Alexander W. Mann, AI Chips: What They Are and Why They Matter, Center for Security & Emerging Technology, Georgetown University, at 10, n.21 (Apr. 2020), https://cset.georgetown.edu/wp-content/uploads/AI-Chips%E2%80%94What-They-Are-and-Why-They-Matter-1.pdf.
4. Jieming Yin et al., Modular Routing Design for Chiplet-Based Systems, in 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA) 726 (2018), https://www.eecg.utoronto.ca/~enright/modular-isca.pdf.
5. Gabriel H. Loh, Samuel Naffziger & Kevin Lepak, Understanding Chiplets Today to Anticipate Future Integration Opportunities and Limits, Design, Automation & Test in Europe Conference 142, 144 (2021), https://www.crosstalk.com/wp-content/uploads/AI-Chips%E2%80%94What-They-Are-and-Why-They-Matter-1.pdf.
6. Zhuoping Yang et al., Challenges and Opportunities to Enable Large-Scale Computing via Heterogeneous Chiplets, 2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA) (forthcoming), https://doi.org/10.48550/arXiv.2311.16417, available at , 2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA) (forthcoming), https://doi.org/10.48550/arXiv.2311.16417, available at https://past.date-conference.com/proceedings-archive/2021/pdf/2001.pdf.
7. UCIE Consortium, Universal Chiplet Interconnect Express, https://www.uciexpress.org/.
8. UCIE Consortium, Specifications, https://www.uciexpress.org/specifications.
9. See, e.g., Brian Holden, Using Chiplets to Lower Package Loss (IEEE P802.3ck 100 Gb/s, 200 Gb/s and 400 Gb/s Electrical Interfaces Task Force Interim Meeting, Pittsburgh, Pa., May 24, 2018) at slide 15, https://www.ieee802.org/3/ck/public/18_05/holden_3ck_01_0518.pdf.
10. Intel Corp., Introducing the Intel Foundry Chiplet Alliance (2025), https://download.intel.com/newsroom/2025/foundry/Intel-DC-Chiplet-Alliance-Partner-Quotes.pdf.
11. Chiplet Alliance, Intel (Apr. 29, 2025), https://www.intel.com/content/www/us/en/foundry/accelerator/chiplet‑, Intel (Apr. 29, 2025), https://www.intel.com/content/www/us/en/foundry/accelerator/chiplet‑alliance.html.
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