United States: Board Exceeded Its "Limited Role" In Reviewing Examiner’s Findings During Reexamination

In Rambus Inc. v. Rea, No. 12-1634 (Fed. Cir. Sept. 24, 2013), the Federal Circuit reviewed an invalidity decision made by the Board during reexamination proceedings.  The Court affirmed the Board's claim construction, vacated the Board's obviousness decision, and remanded for further proceedings.

U.S. Patent No. 6,260,097 ("the '097 patent") is directed to a dynamic random-access memory ("DRAM") that uses a synchronous memory system to transfer data.  In synchronous systems, a clock signal alternates between a digital value of 0 and 1.  The change in the clock signal from 0 to 1 is referred to as the "rising edge" of the clock, and the change in the signal from 1 to 0 is referred to as the "falling edge" of the clock.  In conventional synchronous memory systems, the data transmitted to the memory tie up the system for a full cycle of the clock.  The '097 patent is directed to a system that transfers a portion of the data on the rising edge and a portion of the data on the falling edge of the clock signal, transferring data at twice the rate.

The PTO initiated inter partes reexamination of the '097 patent claims and found that the reexamined claims were not patentable over two references:  Unexamined Japanese Patent Application
No. 56-88987 ("Inagaki") and the Intel iAPX system manual and specification ("iAPX").  The examiner rejected the claims as anticipated by Inagaki and/or obvious in light of the iAPX system in view of Inagaki.  The Board upheld the examiner's rejections, and Rambus appealed.

Regarding anticipation, the Federal Circuit first considered whether the Board properly construed "external clock signal" as requiring the clock to be periodic during the data input phases, as opposed to being periodic for all system operations.  Rambus contended that the intrinsic record required the "external clock signal" to be continuously periodic.  The PTO countered that the claim language required only that the external clock signal synchronize data transfer and need not be periodic for all time.  The Federal Circuit agreed with the PTO that the claimed method required that the "external clock signal" be periodic during data transfer, but that nothing in the claim language, specification, or prosecution history required the signal to be periodic for all time.

"The Board has a procedure for issuing a new ground of rejection in appeals of inter partes reexaminations.  37 C.F.R. § 41.77(b).  This procedure ensures that appellants have an appropriate opportunity to respond and, if necessary, supplement the record before the examiner.  We cannot let the Board shortcut this procedure and deprive appellants of their due process rights."  Slip op. at 12-13.

Next, considering the construction of "write request," the Court agreed with the Board that the claimed "write request" was not limited to a multiple-bit request and could contain a single bit.  Rambus argued that the specification showed that each request carried at least two bits of information.  Rambus also argued that the Board's construction did not comport with the Federal Circuit's holding in a prior case involving the same family of patents as the '097 patent, Rambus Inc. v. Infineon Technologies AG, 318 F.3d 1081, 1093 (Fed. Cir. 2003).

The Court, however, found that the plain language of the claims-at-issue did not limit "write request" to a multiple-bit request, and that the specification disclosed a preferred embodiment involving a single bit.  Although the Court noted that, in rare cases, a claim construction may exclude the preferred embodiment when there is highly persuasive evidentiary support, it concluded that there was no such evidentiary support here.  Moreover, the Court did not find that the Board disregarded the Court's construction in Infineon.  The Court explained that in Infineon, the dispute centered on the accused infringer's contention that the claimed "request" must include both address and control information, and at no time did the Court resolve whether the "write request" can be a single bit.  Slip op. at 7 (citing Infineon, 318 F.3d at 1091).

Because the Federal Circuit concluded that the Board correctly construed the "external signal" and "write request" limitations, it affirmed the Board's finding that Inagaki anticipates claims 1, 2, 7, 8, 10, and 14 of the '097 patent.

With regard to the Board's finding of obviousness, Rambus argued that the Board committed multiple errors, and the Federal Circuit agreed.  First, the Court agreed that the Board erroneously placed the burden on Rambus to show nonobviousness.  The Court stressed that "[i]n reexamination proceedings, 'a preponderance of the evidence must show nonpatentability before the PTO may reject the claims of a patent application.'"  Id. at 10-11 (quoting Ethicon, Inc. v. Quigg, 849 F.2d 1422, 1427 (Fed. Cir. 1988)).  The Court found that the Board concluded that Rambus had not demonstrated nonobviousness, which was legal error.

The Court also found that the Board exceeded its limited role to review the examiner's decisions during prosecution.  The Court explained that the legal framework under the APA limits the Board's ability to rely on different grounds than the examiner in making rejections.  According to the Court, "[t]he ultimate criterion is whether the appellant has had before the PTO a 'fair opportunity to react to the thrust of the rejection.'"  Id. at 11-12 (quoting In re Jung, 637 F.3d 1356, 1365 (Fed. Cir. 2011)).  The Court found the Board erred in supplying its own reasons for combining iAPX and Inagaki after recognizing that the examiner's finding was erroneous.  The Court decided that since the Board has a procedure for issuing a new ground of rejection in appeals of inter partes reexaminations, it could not "let the Board shortcut this procedure and deprive appellants of their due process rights."  Id. at 13.

The Court also held that the Board erred in its treatment of objective evidence of nonobviousness.  Particularly, the Court noted that the Board erroneously ignored Rambus's uncontested evidence of
long-felt need and industry praise due to the claimed dual-edge data transfer functionality and found the evidence lacked a nexus.  Further, the Court emphasized that objective evidence of nonobviousness need only be reasonably commensurate with the scope of the claims, which "do[es] not require a patentee to produce objective evidence of nonobviousness for every potential embodiment of the claim."  Id. at 14.  Accordingly, the Court decided that the Board erred in finding that Rambus's evidence relating to the high-speed memory system embodiments was not commensurate with the scope of the claims.

Additionally, the Court concluded that Rambus's licensing evidence linked its commercial success to the claimed dual-edge data transfer functionality and that the Board's finding of lack of a nexus was unsupported and erroneous.  Ultimately, the Court emphasized that "[w]hile objective evidence of nonobviousness lacks a nexus if it exclusively relates to a feature that was 'known in the prior art,' the obviousness inquiry centers on whether 'the claimed invention as a whole' should have been obvious."  Id. at 15 (citations omitted).  Despite the Board's finding that Rambus's objective evidence of nonobviousness pertained to the claimed dual-edge functionality that was disclosed in Inagaki and known in the prior art, the Court found that at least some of Rambus's evidence relates to Rambus's overall memory device architecture.  Therefore, the Court instructed the Board to carefully consider the objective evidence of nonobviousness on Rambus's patented design as a whole and make the final determination on remand.

Judges:  Moore (author), Linn, O'Malley

[Appealed from Board]

This article previously appeared in Last Month at the Federal Circuit, October 2013.

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